1. Field of the Invention
The present invention relates to a method and system for designing an electronic circuit an more particularly, to a method and system for designing an electronic circuit which includes identifying candidate bins (e.g., bins which may be placement-congested and timing-critical) and performing an area reduction (e.g., area recovery or area optimization) on the candidate bins.
2. Description of the Related Art
Two important processes within logic and physical synthesis of electronic designs are timing correction, in which paths that do not meet the design's timing criteria are sped up, and area reduction, in which the total space used on the image is reduced.
It is a fact of circuit design that circuit speed can be improved if circuit area is increased, and circuit area can be improved if circuit speed is decreased. In timing-critical portions of the design, optimizations such as resizing and cell decomposition increase area and reduce delay. In non-timing-critical areas (e.g., cells having a positive slack, or slack greater than some predetermined amount (the slack threshold)), the reverse optimizations can be done to reduce area at the cost of delay.
For example, on timing-critical paths, delay can be improved by decomposing a 4-way AND into a tree of 2-way ANDs at the cost of area, while on non-critical timing paths, the tree of 2-way ANDs can be merged into a 4-way AND, reducing area but costing speed.
Even though area reduction has beneficial effects on power and wireability, it is often used lightly if at all in physical synthesis. This is partly because timing is of paramount concern, but another reason is that area reduction can be computationally expensive. On an average design, the non-timing-critical portion of the design is vastly larger than the timing-critical part, so area recovery must work on many more cells than does timing correction and may consequently use a lot of computing time.
In a placed design, every cell is assigned a location on the chip image. The space utilization over the design is not necessarily uniform. That is, there are likely some regions where the cells are tightly packed and there is almost no extra room, and some other regions that are very sparsely used.
In addition, timing-critical and non-timing critical cells are also likely intermixed in physical regions of the chip. That is, non-timing-critical cells may be placed near or adjacent to timing-critical cells. Therefore, timing optimizations, which as noted above, require extra area, may be inhibited by the inability to find placement space for the enlarged portion of the design.